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数字电路实验——数字钟设计
最近更新：2024-09-23   |   字数总计：3.9k   |   阅读估时：22分钟   |   阅读量：次
  1. 主体结构代码
    1. 1000Hz 时钟分频模块
    2. 1Hz 时钟分频模块
    3. 按键防抖模块
    4. 秒钟计数模块
    5. 分钟计数模块
    6. 时钟计数模块
    7. 时、分、秒计数模块
    8. 12 小时制-24 小时制切换模块
    9. 屏幕显示模式切换模块
    10. 位选模块
    11. 七段数码管译码模块
    12. 闹钟设置模块
    13. 闹钟触发流水灯模块
    14. 整点报时模块
    15. 数字钟顶层模块
  2. 管脚定义

说明：使用开发板为Nexys4 DDR，仅供交流学习使用，由于时间仓促，可能存在结构不清晰、逻辑不严密等问题，欢迎邮件联系交流。

主体结构代码

1000Hz 时钟分频模块

介绍：

该模块将原本的 100MHz 的时钟频率分频为 1000Hz，并传出给状态转换模块使用。

源码：

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module cp_1000hz(
  input CP,
  output reg CLK = 0
);
  reg [15:0] state;

  always @(posedge CP) begin
    if (state < 49999)
      state <= state + 1'b1;
    else begin
      CLK <= ~CLK;
      state <= 0;
    end
  end
endmodule

1Hz 时钟分频模块

介绍：

该模块将原本的 100MHz 的时钟频率分频为 1Hz，并传出给状态转换模块使用。

源码：

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module cp_1hz(
input CP,
output reg CLK = 0
);
reg [31:0] state;

always @(posedge CP) begin
if (state < 49999999)
state <= state + 1'b1;
else begin
CLK <= ~CLK;
state <= 0;
end
end
endmodule

按键防抖模块

介绍：

该模块可以对按键进行防抖动处理。

源码：

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module FDD (
input wire clk,
input wire button_in,
input wire CHO_SET,
output reg jia_min = 0,
output reg jia_hour = 0
);

reg [3:0] debounce_reg = 4'b0000;

always @(posedge clk) begin
debounce_reg <= {debounce_reg[2:0], button_in};

if (debounce_reg == 4'b0000)begin
if(CHO_SET)begin
jia_hour <= 0;
end
else if(~CHO_SET)begin
jia_min <= 0;
end
end
else if (debounce_reg == 4'b1111)begin
if(CHO_SET)begin
jia_hour <= 1;
end
else if(~CHO_SET)begin
jia_min <= 1;
end
end
end
endmodule

秒钟计数模块

介绍：

该模块可以实现秒钟的计数，并返回分钟的进位信号。

源码：

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module COUNT_miao(
input wire clk,
input wire reset,
output reg [3:0] miao_shi,
output reg [3:0] miao_ge,
output reg miao_jin = 0
);

always @(posedge clk or negedge reset) begin
if (~reset) begin
miao_shi <= 4'b0000;
miao_ge  <= 4'b0000;
end
else begin
if (miao_ge == 4'b1001) begin
miao_ge <= 4'b0000;
if (miao_shi == 4'b0101) begin
miao_shi <= 4'b0000;
miao_jin <= 1'b1;
end
else begin
miao_shi <= miao_shi + 4'b0001;
miao_jin <= 1'b0;
end
end
else begin
miao_ge <= miao_ge + 4'b0001;
miao_jin <= 1'b0;
end
end
end
endmodule

分钟计数模块

介绍：

该模块可以实现分钟的计数，并返回时钟的进位信号，还可以通过改变驱动源来切换到计时模式和调时模式。

源码：

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module COUNT_min(
input wire reset,
input wire miao_jin,
input wire jiajian_min,
input wire jiajian,
input wire TJ_clock,
output reg [3:0] min_shi,
output reg [3:0] min_ge,
output reg min_jin = 0
);

reg min_clock=0;
always@(*)begin
if(~TJ_clock)begin
min_clock <= miao_jin;
end
else if(TJ_clock)begin
min_clock <= jiajian_min;
end
end


always @(negedge reset or posedge min_clock) begin
if (~reset) begin
min_shi <= 4'b0000;
min_ge  <= 4'b0000;
end
else if(jiajian && TJ_clock) begin
if (min_ge == 4'b1001) begin
min_ge <= 4'b0000;
if (min_shi == 4'b0101) begin
min_shi <= 4'b0000;
min_jin <= 1'b1;
end
else begin
min_shi <= min_shi + 4'b0001;
min_jin <= 1'b0;
end
end
else begin
min_ge <= min_ge + 4'b0001;
min_jin <= 1'b0;
end
end

else if(~jiajian && TJ_clock)begin
if (min_ge == 4'b0000 && min_shi > 4'b0000) begin
min_ge <= 4'b1001;
min_shi <= min_shi - 4'b0001;
end
else if(min_ge>0)begin
min_ge <= min_ge - 4'b0001;
end
end

else begin
if (min_ge == 4'b1001) begin
min_ge <= 4'b0000;
if (min_shi == 4'b0101) begin
min_shi <= 4'b0000;
min_jin <= 1'b1;
end
else begin
min_shi <= min_shi + 4'b0001;
min_jin <= 1'b0;
end
end
else begin
min_ge <= min_ge + 4'b0001;
min_jin <= 1'b0;
end
end
end
endmodule

时钟计数模块

介绍：

该模块可以实现时钟的计数，并且可以通过改变驱动源来切换到计时模式和调时模式。

源码：

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module COUNT_hour(
input wire reset,
input wire min_jin,
input wire jiajian_hour,
input wire jiajian,
input wire TJ_clock,
output reg [3:0] hour_shi,
output reg [3:0] hour_ge
);
reg hour_clock=0;
always@(*)begin
if(~TJ_clock)begin
hour_clock <= min_jin;
end
else if(TJ_clock)begin
hour_clock <= jiajian_hour;
end

end

always @(negedge reset or posedge hour_clock) begin
if (~reset) begin
hour_shi <= 4'b0000;
hour_ge  <= 4'b0000;
end
else if(jiajian && TJ_clock) begin
if (hour_ge == 4'b0011 && hour_shi == 4'b0010) begin
hour_ge <= 4'b0000;
hour_shi <= 4'b0000;
end
else if (hour_ge == 4'b1001) begin
hour_ge <= 4'b0000;
hour_shi <= hour_shi + 4'b0001;
end
else begin
hour_ge <= hour_ge + 4'b0001;
end
end
else if(~jiajian && TJ_clock) begin
if (hour_ge == 4'b0000 && hour_shi > 4'b0000) begin
hour_ge <= 4'b1001;
hour_shi <= hour_shi - 4'b0001;
end
else if(hour_ge>0)begin
hour_ge <= hour_ge - 4'b0001;
end
end
else begin
if (hour_ge == 4'b0011 && hour_shi == 4'b0010) begin
hour_ge <= 4'b0000;
hour_shi <= 4'b0000;
end
else if (hour_ge == 4'b1001) begin
hour_ge <= 4'b0000;
hour_shi <= hour_shi + 4'b0001;
end
else begin
hour_ge <= hour_ge + 4'b0001;
end
end
end
endmodule

时、分、秒计数模块

介绍：

该模块是时、分、秒三个计数模块的顶层模块，将三个计时模块连接起来形成一个统一的模块，实现层次化设计。

源码：

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module COUNT(
input wire clk,
input wire reset,
input wire jiajian_hour,
input wire jiajian_min,
input wire jiajian,
input wire TJ_clock,
output wire [3:0] hour_shi,
output wire [3:0] hour_ge,
output wire [3:0] min_shi,
output wire [3:0] min_ge,
output wire [3:0] miao_shi,
output wire [3:0] miao_ge
);

wire miao_jin;
wire min_jin;

COUNT_miao COUNT_miao_inst(
.reset(reset),
.clk(clk),
.miao_shi(miao_shi),
.miao_ge(miao_ge),
.miao_jin(miao_jin)
);

COUNT_min COUNT_min_inst(
.reset(reset),
.min_shi(min_shi),
.min_ge(min_ge),
.miao_jin(miao_jin),
.min_jin(min_jin),
.jiajian_min(jiajian_min),
.jiajian(jiajian),
.TJ_clock(TJ_clock)
);

COUNT_hour COUNT_hour_inst(
.reset(reset),
.hour_shi(hour_shi),
.hour_ge(hour_ge),
.jiajian_hour(jiajian_hour),
.jiajian(jiajian),
.TJ_clock(TJ_clock),
.min_jin(min_jin)
);
endmodule

12 小时制-24 小时制切换模块

介绍：

该模块可以实现 12 小时制与 24 小时制的切换。

源码：

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module TO24_12(
input wire cho24_12,
input wire [3:0] hour_shi_in,
input wire [3:0] hour_ge_in,
output reg [3:0] hour_shi_out,
output reg [3:0] hour_ge_out,
output reg [3:0] P_A
);

always @(*)begin
if(~cho24_12)begin
if ((hour_shi_in == 4'b0001 && hour_ge_in > 4'b0010) || (hour_shi_in > 4'b0001)) begin
if(hour_shi_in == 4'b0010 && hour_ge_in == 4'b0000)begin
hour_shi_out <= 4'b0000;
hour_ge_out  <= 4'b1000;
P_A <= 4'b1111;
end
else if(hour_shi_in == 4'b0010 && hour_ge_in ==  4'b0001)begin
hour_shi_out <= 4'b0000;
hour_ge_out  <= 4'b1001;
P_A <= 4'b1111;
end
else begin
hour_shi_out <= hour_shi_in - 4'b0001;
hour_ge_out  <= hour_ge_in - 4'b0010;
P_A <= 4'b1111;
end
end

else begin
hour_shi_out <= hour_shi_in;
hour_ge_out  <= hour_ge_in;
P_A <= 4'b1110;
end
end
if(cho24_12)begin
hour_shi_out <= hour_shi_in;
hour_ge_out  <= hour_ge_in;
P_A <= 4'b1011;
end
end
endmodule

屏幕显示模式切换模块

介绍：

该模块可以在时钟模式与闹钟模式两种显示模式之间切换。

源码：

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module mode(
input wire mode,
input wire [3:0] P_A,
input wire [3:0] hour_shi,
input wire [3:0] hour_ge,
input wire [3:0] min_shi,
input wire [3:0] min_ge,
input wire [3:0] miao_shi,
input wire [3:0] miao_ge,
input wire [3:0] hour_shi_alarm,
input wire [3:0] hour_ge_alarm,
input wire [3:0] min_shi_alarm,
input wire [3:0] min_ge_alarm,
output reg [3:0] hour_shi_top,
output reg [3:0] hour_ge_top,
output reg [3:0] min_shi_top,
output reg [3:0] min_ge_top,
output reg [3:0] miao_shi_top,
output reg [3:0] miao_ge_top,
output reg [3:0] P_A_top
);

always @(*)begin
if(~mode)begin
hour_shi_top <= hour_shi;
hour_ge_top  <= hour_ge;
min_shi_top  <= min_shi;
min_ge_top   <= min_ge;
miao_shi_top <= miao_shi;
miao_ge_top  <= miao_ge;
P_A_top      <= P_A;
end
else if(mode)begin
hour_shi_top <= hour_shi_alarm;
hour_ge_top  <= hour_ge_alarm;
min_shi_top  <= min_shi_alarm;
min_ge_top   <= min_ge_alarm;
miao_shi_top <= 4'b0000;
miao_ge_top  <= 4'b0000;
P_A_top      <= 4'b1100;
end
end
endmodule

位选模块

介绍：

该模块可以实现 1000Hz 频率下的七段数码管的循环位选。

源码：

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module SEG_CHO (
input wire clk_1000hz,
input wire [3:0] hour_shi,
input wire [3:0] hour_ge,
input wire [3:0] min_shi,
input wire [3:0] min_ge,
input wire [3:0] miao_shi,
input wire [3:0] miao_ge,
input wire [3:0] P_A,
output reg [7:0] seg_cho,
output reg [3:0] seg
);
reg [2:0] counter = 3'b000;

always@(posedge clk_1000hz)
begin
case(counter)
3'b000:
begin
seg_cho <= 8'b11111110;
seg <= miao_ge;
counter <= counter+3'b001;
end
3'b001:
begin
seg_cho <= 8'b11111101;
seg <= miao_shi;
counter <= counter+3'b001;
end
3'b010:
begin
seg_cho <= 8'b11111011;
seg <= min_ge;
counter <= counter+3'b001;
end
3'b011:
begin
seg_cho <= 8'b11110111;
seg <= min_shi;
counter <= counter+3'b001;
end
3'b100:
begin
seg_cho <= 8'b11101111;
seg <= hour_ge;
counter <= counter+3'b001;
end
3'b101:
begin
seg_cho <= 8'b11011111;
seg <= hour_shi;
counter <= counter+3'b001;
end
3'b110:
begin
seg_cho <= 8'b10111111;
seg <= 4'b1011;
counter <= counter+3'b001;
end
3'b111:
begin
seg_cho <= 8'b01111111;
seg <= P_A;
counter <= 3'b000;
end
endcase

end

endmodule

七段数码管译码模块

介绍：

该模块可以实现对输入信号到七段数码管显示信号的译码。

源码：

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module SEG(
input [3:0] IN,
output reg[6:0] show=0
);
always@(IN)
begin
case(IN)
4'b0000:show<=7'b100_0000;
4'b0001:show<=7'b111_1001;
4'b0010:show<=7'b010_0100;
4'b0011:show<=7'b011_0000;
4'b0100:show<=7'b001_1001;
4'b0101:show<=7'b001_0010;
4'b0110:show<=7'b000_0010;
4'b0111:show<=7'b111_1000;
4'b1000:show<=7'b000_0000;
4'b1001:show<=7'b001_0000;
4'b1110:show<=7'b000_1000;
4'b1111:show<=7'b000_1100;
default:show<=7'b111_1111;
endcase
end
endmodule

闹钟设置模块

介绍：

该模块可以设置该时钟的闹钟，当计时模块的时钟和分钟与闹钟设置的相同时，会触发闹钟，即流水灯。

源码：

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module alarm(
input clk,
input button_in_alarm,
input jiajian_alarm,
input CHO_SET_alarm,
output reg [3:0] hour_shi_alarm = 4'b0000,
output reg [3:0] hour_ge_alarm = 4'b0000,
output reg [3:0] min_shi_alarm = 4'b0000,
output reg [3:0] min_ge_alarm = 4'b0000
);

reg min_clock_alarm = 0;
reg hour_clock_alarm = 0;
reg [3:0] debounce_reg_alarm = 4'b0000;

always @(posedge clk) begin
debounce_reg_alarm <= {debounce_reg_alarm[2:0], button_in_alarm};

if (debounce_reg_alarm == 4'b0000)begin
if(CHO_SET_alarm)begin
hour_clock_alarm <= 0;
end
else if(~CHO_SET_alarm)begin
min_clock_alarm <= 0;
end
end
else if (debounce_reg_alarm == 4'b1111)begin
if(CHO_SET_alarm)begin
hour_clock_alarm <= 1;
end
else if(~CHO_SET_alarm)begin
min_clock_alarm <= 1;
end
end
end

always @(posedge min_clock_alarm) begin
if(jiajian_alarm) begin
if (min_ge_alarm == 4'b1001) begin
min_ge_alarm <= 4'b0000;
if (min_shi_alarm == 4'b0101) begin
min_shi_alarm <= 4'b0000;
end
else begin
min_shi_alarm <= min_shi_alarm + 4'b0001;
end
end
else begin
min_ge_alarm <= min_ge_alarm + 4'b0001;
end
end

else if(~jiajian_alarm)begin
if (min_ge_alarm == 4'b0000 && min_shi_alarm > 4'b0000) begin
min_ge_alarm <= 4'b1001;
min_shi_alarm <= min_shi_alarm - 4'b0001;
end
else if(min_ge_alarm>0)begin
min_ge_alarm <= min_ge_alarm - 4'b0001;
end
end

end

always @(posedge hour_clock_alarm) begin
if(jiajian_alarm) begin
if (hour_ge_alarm == 4'b0011 && hour_shi_alarm == 4'b0010) begin
hour_ge_alarm <= 4'b0000;
hour_shi_alarm <= 4'b0000;
end
else if (hour_ge_alarm == 4'b1001) begin
hour_ge_alarm <= 4'b0000;
hour_shi_alarm <= hour_shi_alarm + 4'b0001;
end
else begin
hour_ge_alarm <= hour_ge_alarm + 4'b0001;
end
end
else if(~jiajian_alarm) begin
if (hour_ge_alarm == 4'b0000 && hour_shi_alarm > 4'b0000) begin
hour_ge_alarm <= 4'b1001;
hour_shi_alarm <= hour_shi_alarm - 4'b0001;
end
else if(hour_ge_alarm>0)begin
hour_ge_alarm <= hour_ge_alarm - 4'b0001;
end
end
else begin
if (hour_ge_alarm == 4'b0011 && hour_shi_alarm == 4'b0010) begin
hour_ge_alarm <= 4'b0000;
hour_shi_alarm <= 4'b0000;
end
else if (hour_ge_alarm == 4'b1001) begin
hour_ge_alarm <= 4'b0000;
hour_shi_alarm <= hour_shi_alarm + 4'b0001;
end
else begin
hour_ge_alarm <= hour_ge_alarm + 4'b0001;
end
end
end
endmodule

闹钟触发流水灯模块

介绍：

当闹钟被触发后，该模块使能，即流水灯开始工作。

源码：

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module alarm_led(
input wire clk,      // 时钟信号
input wire [3:0] hour_shi_alarm,
input wire [3:0] hour_ge_alarm,
input wire [3:0] min_shi_alarm,
input wire [3:0] min_ge_alarm,
input wire [3:0] hour_shi,
input wire [3:0] hour_ge,
input wire [3:0] min_shi,
input wire [3:0] min_ge,
output reg [15:0] led_out // LED输出信号
);

reg [3:0] counter = 4'b0000;      // 计数器
reg [15:0] led;   // 移位寄存器
wire [15:0] num_alarm;
wire [15:0] num;

assign num_alarm = {hour_shi_alarm, hour_ge_alarm, min_shi_alarm, min_ge_alarm};
assign num = {hour_shi, hour_ge, min_shi, min_ge};

reg [15:0] state = 0;
reg clk_5hz = 0;

always @(posedge clk) begin
if (state < 49)
state <= state + 1'b1;
else begin
clk_5hz <= ~clk_5hz;
state <= 0;
end
end

always @(posedge clk_5hz) begin
if (counter == 4'b1111)begin
counter <= 4'b0000; // 计数器满时重置
end
else begin
counter <= counter + 1; // 递增计数器
end

case(counter)
4'b0000:led<=16'b0000000000000011;
4'b0001:led<=16'b0000000000000111;
4'b0010:led<=16'b0000000000001111;
4'b0011:led<=16'b0000000000011111;
4'b0100:led<=16'b0000000000111111;
4'b0101:led<=16'b0000000001111100;
4'b0110:led<=16'b0000000011111000;
4'b0111:led<=16'b0000000111110000;
4'b1000:led<=16'b0000001111100000;
4'b1001:led<=16'b0000011111000000;
4'b1010:led<=16'b0000111110000000;
4'b1011:led<=16'b0001111100000000;
4'b1100:led<=16'b0011111000000000;
4'b1101:led<=16'b0111110000000000;
4'b1110:led<=16'b1111100000000000;
4'b1111:led<=16'b1111000000000001;
default:led<=16'b1111111111111111;
endcase
if(num == num_alarm)begin
led_out <= led;
end
else begin
led_out <= 16'b0000000000000000;
end
end
endmodule

整点报时模块

介绍：

该模块可以实现整点报时，而且灯闪烁的次数与当前的小时制有关，即闪烁次数总是与时钟正在显示的值相同。当下午 5 点报时，若为 12 小时制，则闪烁 5 次；若为 24 小时制，则闪烁 17 次。

源码：

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module ZDBS(
input wire clk,
input wire [3:0] hour_shi,
input wire [3:0] hour_ge,
input wire [3:0] min_shi,
input wire [3:0] min_ge,
input wire [3:0] miao_shi,
input wire [3:0] miao_ge,
output reg zdbs_led = 0
);

reg [3:0] hour_shi_dec;
reg [3:0] hour_ge_dec;
reg [7:0] num = 8'b0000000;
reg [7:0] num_count = 8'b0000000;
reg [15:0] state = 0;
reg clk_5hz = 0;

always @(*) begin
case(hour_shi)
4'b0000: hour_shi_dec = 0;
4'b0001: hour_shi_dec = 1;
4'b0010: hour_shi_dec = 2;
4'b0011: hour_shi_dec = 3;
default: hour_shi_dec = 0;  // 默认值
endcase

case(hour_ge)
4'b0000: hour_ge_dec = 0;
4'b0001: hour_ge_dec = 1;
4'b0010: hour_ge_dec = 2;
4'b0011: hour_ge_dec = 3;
4'b0100: hour_ge_dec = 4;
4'b0101: hour_ge_dec = 5;
4'b0110: hour_ge_dec = 6;
4'b0111: hour_ge_dec = 7;
4'b1000: hour_ge_dec = 8;
4'b1001: hour_ge_dec = 9;
default: hour_ge_dec = 0;  // 默认值
endcase
end

always @(posedge clk) begin
if (state < 149)
state <= state + 1'b1;
else begin
clk_5hz <= ~clk_5hz;
state <= 0;
end
end

always @(posedge clk_5hz) begin
num <= hour_shi_dec * 10 + hour_ge_dec;
if((min_shi == 4'b0000) && (min_ge == 4'b0000) && (miao_shi == 4'b0000) && (miao_ge == 4'b0000)&& (num_count == 8'b00000000))begin
num_count <= (num + 1) * 2;
end

if(num_count != 8'b00000000)begin
zdbs_led <= ~zdbs_led;
num_count <= num_count - 1;
end
end

endmodule

数字钟顶层模块

介绍：

该模块将所有模块按照逻辑顺序依次连接，形成统一整体。

源码：

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module SZZ_TOP(
input CP,reset,button_in,button_in_alarm,
input CHO_SET,CHO_SET_alarm,
input TJ_clock,jiajian,jiajian_alarm,
input mode,
input cho24_12,
output [6:0]SEG_Out,
output [7:0]SEG_CHO,
output [15:0] led_out,
output zdbs_led
);
wire CLK_1hz;
wire CLK_1000hz;
wire [3:0] hour_shi_24to12;
wire [3:0] hour_ge_24to12;
wire [3:0] P_A;
wire [3:0] P_A_top;
wire [3:0] hour_shi;
wire [3:0] hour_ge;
wire [3:0] min_shi;
wire [3:0] min_ge;
wire [3:0] miao_shi;
wire [3:0] miao_ge;
wire [3:0] seg;
wire jia_min,jia_hour;

wire [3:0] hour_shi_alarm;
wire [3:0] hour_ge_alarm;
wire [3:0] min_shi_alarm;
wire [3:0] min_ge_alarm;

wire [3:0] hour_shi_top;
wire [3:0] hour_ge_top;
wire [3:0] min_shi_top;
wire [3:0] min_ge_top;
wire [3:0] miao_shi_top;
wire [3:0] miao_ge_top;

TO24_12 TO24_12_inst(
.cho24_12(cho24_12),
.hour_shi_in(hour_shi_24to12),
.hour_ge_in(hour_ge_24to12),
.hour_shi_out(hour_shi),
.hour_ge_out(hour_ge),
.P_A(P_A)
);

ZDBS ZDBS_inst(
.clk(CLK_1000hz),
.hour_shi(hour_shi),
.hour_ge(hour_ge),
.min_shi(min_shi),
.min_ge(min_ge),
.miao_shi(miao_shi),
.miao_ge(miao_ge),
.zdbs_led(zdbs_led)
);

alarm_led alarm_led_inst(
.clk(CLK_1000hz),
.hour_shi_alarm(hour_shi_alarm),
.hour_ge_alarm(hour_ge_alarm),
.min_shi_alarm(min_shi_alarm),
.min_ge_alarm(min_ge_alarm),
.hour_shi(hour_shi_24to12),
.hour_ge(hour_ge_24to12),
.min_shi(min_shi),
.min_ge(min_ge),
.led_out(led_out)
);

alarm alarm_indust(
.clk(CLK_1000hz),
.button_in_alarm(button_in_alarm),
.jiajian_alarm(jiajian_alarm),
.CHO_SET_alarm(CHO_SET_alarm),
.hour_shi_alarm(hour_shi_alarm),
.hour_ge_alarm(hour_ge_alarm),
.min_shi_alarm(min_shi_alarm),
.min_ge_alarm(min_ge_alarm)
);

mode mode_inst(
.mode(mode),
.hour_shi(hour_shi),
.hour_ge(hour_ge),
.min_shi(min_shi),
.min_ge(min_ge),
.miao_shi(miao_shi),
.miao_ge(miao_ge),
.hour_shi_alarm(hour_shi_alarm),
.hour_ge_alarm(hour_ge_alarm),
.min_shi_alarm(min_shi_alarm),
.min_ge_alarm(min_ge_alarm),
.hour_shi_top(hour_shi_top),
.hour_ge_top(hour_ge_top),
.min_shi_top(min_shi_top),
.min_ge_top(min_ge_top),
.miao_shi_top(miao_shi_top),
.miao_ge_top(miao_ge_top),
.P_A(P_A),
.P_A_top(P_A_top)
);

FDD FDD_inst(
.clk(CLK_1000hz),
.button_in(button_in),
.CHO_SET(CHO_SET),
.jia_min(jia_min),
.jia_hour(jia_hour)
);

cp_1hz CP_1hz(
.CP(CP),
.CLK(CLK_1hz)
);
cp_1000hz CP_1000hz(
.CP(CP),
.CLK(CLK_1000hz)
);
COUNT COUNT_inst(
.reset(reset),
.clk(CLK_1hz),
.hour_shi(hour_shi_24to12),
.hour_ge(hour_ge_24to12),
.min_shi(min_shi),
.min_ge(min_ge),
.miao_shi(miao_shi),
.miao_ge(miao_ge),
.jiajian_hour(jia_hour),
.jiajian_min(jia_min),
.jiajian(jiajian),
.TJ_clock(TJ_clock)
);

SEG_CHO SEG_CHO_inst(
.clk_1000hz(CLK_1000hz),
.hour_shi(hour_shi_top),
.hour_ge(hour_ge_top),
.min_shi(min_shi_top),
.min_ge(min_ge_top),
.miao_shi(miao_shi_top),
.miao_ge(miao_ge_top),
.seg_cho(SEG_CHO),
.P_A(P_A_top),
.seg(seg)
);

SEG SEG_inst(
.IN(seg),
.show(SEG_Out)
);

endmodule

管脚定义

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set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports reset]
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports cho24_12]
set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { TJ_clock }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { CHO_SET }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { jiajian }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { mode }]; #IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { CHO_SET_alarm }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { jiajian_alarm }]; #IO_L5N_T0_D07_14 Sch=sw[7]

set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { led_out[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { led_out[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { led_out[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { led_out[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { led_out[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { led_out[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { led_out[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { led_out[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { led_out[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { led_out[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { led_out[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { led_out[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { led_out[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { led_out[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { led_out[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { led_out[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]

set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { zdbs_led }]; #IO_L10P_T1_D14_14 Sch=led16_g

set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CP]

set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports button_in]
set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { button_in_alarm }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd

set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {SEG_Out[0]}]
set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {SEG_Out[1]}]
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {SEG_Out[2]}]
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {SEG_Out[3]}]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {SEG_Out[4]}]
set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {SEG_Out[5]}]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {SEG_Out[6]}]

set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {SEG_CHO[0]}]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {SEG_CHO[1]}]
set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {SEG_CHO[2]}]
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {SEG_CHO[3]}]
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {SEG_CHO[4]}]
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {SEG_CHO[5]}]
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {SEG_CHO[6]}]
set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {SEG_CHO[7]}]
#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { test }]; #IO_L19N_T3_A21_VREF_15 Sch=dp

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets cho24_12_IBUF]
2024-06-23 该篇文章被 HolioFox 打上标签: 数字电路实验 归为分类: 硬件

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